So, now when V G = 0V, then V SG is more than V T, and because of that, PMOS will conduct and it will try to bring down the voltage of the source terminal to 0V. And let’s assume that, initially, the voltage across the capacitor is 3V. And capacitor is connected at the source terminal. Let’s say now the drain terminal is connected to ground. NMOS passes weak logic ‘1’ and Strong logic ‘0’Īpart from the power dissipation, the other issue with the NMOS transistor is that, it passes weak logic ‘1’. And the power dissipation becomes a critical factor when there are millions of such transistors in the circuit. That means when we are designing the logic gates only using NMOS or PMOS transistors then there will be a static power dissipation. That means, if the input to the inverter is a clock signal which is continuously changing between ‘1’ and ‘0’ then for half of the total time, there will be a static power dissipation across the NMOS transistors.Īnd the same is case with the logic gate designed using PMOS transistors. And because of that, there is power dissipation across the NMOS transistor. The issue with this design is that, there is a static power dissipation across the transistor.įor example, when the input to the inverter is ‘1’ then NMOS will be ON, and it provides very low resistance. Of course, by changing the MOSFETs device parameters, it is possible to ensure that, its ON resistance is in kΩ.
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